This invention relates to semiconductor devices comprising a power transistor and a suppression diode connected in series with the power transistor so as to suppress reverse current flow in the transistor. The invention also relates to methods of manufacturing such devices.
Current flow through parasitic diodes within power transistors can be problematic in increasing the switching time and switching losses of the transistor. Known power transistor structures generally have a current path between first and second regions (emitter and collector, or source and drain) that are adjacent to respective front and back, opposite surfaces of the semiconductor body. These first and second regions are connected to respective front and back metallisations. The body is generally mounted on a terminal connection area of the device via the back metallisation. A base region of opposite conductivity type is present in the current path (in between the first and second regions) and forms a p-n junction with an adjacent first part of the second region (collector or drain). This first part has a lower conductivity-type-determining dopant concentration than an underlying second part of the second region.
The problematic parasitic diode in the case of an insulated-gate field-effect transistor (often termed MOSFET) is the base-drain p-n junction. The voltage polarity between source and drain (front and back metallisations) of the MOSFET can temporarily reverse, for example when switching an inductive load. This reversed voltage polarity forward biases the parasitic diode, which may then conduct to give a reverse current flow in the transistor.
Because this diode is a bipolar component, it is subject to charge storage effects. It generally has a slow reverse recovery time, which can cause switching losses in operation of the MOSFET. It is known to suppress turn on of the parasitic diode by connecting an opposed, external diode in series with the transistor. Such a transistor-diode circuit arrangement is illustrated in, for example, FIG. 6 on page 249 of the Power Semiconductors Applications Handbook 1995 of Philips Semiconductors, published December 1994 (1133011/12000/02/; document order no. 9398 652 85011) and is discussed on page 250. This FIG. 6 circuit is part of an A.C. motor control and comprises an inverter formed of two such transistor-diode circuit arrangements each with an additional external diode of fast recovery time coupled in anti-parallel relationship to the transistor-diode circuit arrangement. This fast-recovery anti-parallel diode provides the inverter with a reverse current path external to the MOSFET and in place of the suppressed slow-recovery internal (parasitic) diode of the MOSFET.
Similarly in the case of a bipolar transistor, there is a problematic parasitic diode formed by the base-collector p-n junction. When the bipolar transistor is being switched with an inductive load, this parasitic p-n diode may become forward biased so as to inject minority charge carriers, producing a reverse current flow in the transistor and rendering its base drive less stable. Suppression of this parasitic diode would therefore be advantageous. Furthermore, for example, in deflection circuits for televisions and monitors, an external diode (a clamp or damper diode) may be required in anti-parallel with the bipolar transistor. Such a circuit configuration is illustrated in pages 321 to 329 of the said Power Semiconductors Applications Handbook 1995.
It is an aim of the present invention to provide a convenient arrangement for integrating a diode in series with a power transistor so as to suppress the problematic reverse current flow in the transistor and also for facilitating inclusion of an anti-parallel diode (when required) in the device, at least on the same terminal area of the device as the integrated transistor-diode body.
According to the present invention, there is provided a semiconductor device comprising a semiconductor body in and on which a power transistor and a suppression diode are integrated. The body is mounted on a terminal connection area of the device via the back metallisation. The suppression diode is formed in series with the second (back) region of the power transistor and adjacent to the back surface of the body by a diode junction that is present between the back metallisation and a part of the second region. This diode junction opposes the p-n junction between the second region and the base region so as to suppress reverse current flow in the transistor.
Furthermore, in a device in accordance with the invention, the second region has a sufficient thickness as to prevent any minority charge carriers injected into the second region by the diode junction from reaching the p-n junction with the base region. This thickness is typically at least two or more times larger than a diffusion length for charge carriers of the opposite conductivity type (minority carriers) therein. In many devices, it may be considerably larger (for example, by an order of magnitude) than the minority-carrier diffusion length, and so any minority carriers injected into the second region from the diode will not progress far into the transistor before they recombine with majority carriers in the second region. This thickness may then be the main means for ensuring that no latching (thyristor action) occurs between the diode and the transistor. However the device may also include other technical features that contribute to, or even mainly determine, the prevention of latching. Thus, for example, the diode junction may be so constructed between the back metallisation and the second region of the transistor as to reduce minority carrier injection into the second region.
Several particularly advantageous features and options available with the invention are set out in the appended Claims.
The suppression diode junction may be formed directly with a part of the second region of the transistor. Thus, for example, the back metallisation may provide the suppression diode as a Schottky barrier with the second (back) region, when this region part is not highly doped. An advantage of using a Schottky barrier as the suppression diode is that there is very little injection of minority charge carriers across the Schottky barrier. However, this particular construction can restrict the trade-offs possible between different characteristics of the transistor (for example, the series resistance of the second region) and of the suppression diode (for example, its breakdown voltage).
More versatility can be achieved by including a semiconductor layer on the back surface of the body, between the back surface and the back metallisation. Such a semiconductor layer may have, adjacent to the diode junction, a conductivity-type-determining dopant concentration that is lower than the conductivity-type-determining dopant concentration of the first conductivity type of the adjacent part of the second region.
The lower dopant concentration of the semiconductor layer permits a variety of diode types to be formed with the semiconductor layer. Thus, for example, the adjacent part of the layer having the lower conductivity-type-determining dopant concentration may be of either the first conductivity type or of a second (opposite) conductivity type. The diode may be either a p-n junction diode or a Schottky diode.
Thus, the low doping of the semiconductor layer can allow a Schottky barrier to be formed between the back metallisation and the semiconductor layer, without restricting the doping concentration of the second region of the transistor. By providing such a Schottky barrier as the suppression diode, there is very little injection of minority charge carriers across the diode junction into the semiconductor layer and into the transistor. Thus, there is no significant latch up possibility between the diode and the transistor.
Alternatively, the diode may be formed as a p-n junction with, for example, the second region of the body or with another region within the layer. In this case the lower doping concentration of the layer (adjacent to this p-n junction) reduces minority charge carrier injection into the second region. The p-n junction may be formed at the back surface of the body or within the semiconductor layer. The p-n junction may be parallel to the back surface, or even extend across the thickness of the semiconductor layer between windowed insulating layers.
Typically the dopant concentration of the first conductivity type of the second region may be two or three orders of magnitude higher (i.e. 102 or 103 times higher) than the lower conductivity-type-determining dopant concentration of the semiconductor layer. Under these circumstances in a p-n junction diode, charge carrier injection is predominantly from the second region to the semiconductor layer (and not in the opposite direction), and the minority-carrier diffusion length in the second region can be quite short.
The dopant concentration of the first conductivity type of the adjacent part of the second region may be so much higher than the lower conductivity-type-determining dopant concentration of the semiconductor layer as to be diffused into part of the semiconductor layer. The semiconductor layer may have an interface with the second region over the whole of the back surface of the body, or it may have a more localised interface (at one or more windows in an insulating layer between the semiconductor layer and the back surface of the body ).
Devices in accordance with the present invention have their suppression diode junction integrated in or on the semiconductor body of the transistor, between the back metallisation and the second (back) region of the transistor. This configuration permits an anti-parallel diode to be mounted on the terminal connection area of the device, in side-by-side relationship with the semiconductor body of the transistor. Thus, when the transistor is used in a circuit requiring such an anti-parallel diode, the anti-parallel diode can be included in the same device package as the transistor.
Several of the device structures can also be manufactured advantageously in accordance with the invention.